A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
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10.1-ENOB、6.2-fJ/转换步长、500MS/s、基于 Ringamp 的流水线 SAR ADC，采用 16-nm CMOS 封装，具有背景校准和动态参考调节功能
DOI：
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发表时间：
2022
影响因子：
5.4
通讯作者：
J. Craninckx
中科院分区：
文献类型：
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作者：
J. Lagos;N. Markulić;B. Hershberg;D. Dermit;M. Shrivas;E. Martens;J. Craninckx
这项工作提出了一种单通道，全动态流水线合成孔径雷达ADC，由于使用了环形放大和背景校准，具有轻松的结构权衡。它利用新颖的合成孔径雷达量化器和窄带抖动注入，实现对DAC失配、级间增益、环形放大器(振荡器)线性度和偏置优化的快速、全面的背景校准。ADC还包括一个片内、宽范围、全动态基准电压调节系统。在16 nm CMOS中实现，在500MS/S(含稳压)下功耗3.3 mW，获得10.1ENOB和75.5dBSFDR，Schreier和Walden品质因子值分别为171.1 dB和6.2fJ/cv-Step。
This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.