Performance-driven global routing for cell based ICs
Performance-driven global routing for cell based ICs
复制标题
基于单元的 IC 的性能驱动型全局布线
DOI：
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发表时间：
1991
期刊：
影响因子：
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通讯作者：
Chak
中科院分区：
文献类型：
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作者：
J. Cong;A. Kahng;G. Robins;M. Sarrafzadeh;Chak
VLSI技术的进步和电路设计复杂性的增加使得性能成为布局的越来越重要的约束。在全局布线阶段的延迟优化的问题得到解决。将该问题转化为平面上给定点集的有界半径生成树的构造问题，并给出了一族有效的算法。这种方法具有很好的经验性能方面的总线长，并可以顺利之间的竞争最小延迟和最小总netlength的要求，证实了广泛的计算结果，证实了这一点。扩展可以作出的图形和施泰纳版本的问题，并描述了一些开放的问题。<<ETX>>
Advances in VLSI technology and the increased complexity of circuit designs cause performance to become an increasingly important constraint for layout. The issue of delay optimization during the global routing phase is addressed. This problem is formulated as the construction of a bounded-radius spanning tree for a given pointset in the plane, and a family of effective heuristics is presented. This approach has very good empirical performance with respect to total wirelength, and can be smoothly tuned between the competing requirements of minimum delay and minimum total netlength, as confirmed by extensive computational results which confirm this. Extensions can be made to the graph and Steiner versions of the problem, and a number of open problems are described.<<ETX>>