CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
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DOI：
10.1109/ats.2008.27
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发表时间：
2008-11
期刊：
影响因子：
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通讯作者：
H. Furukawa;X. Wen;K. Miyase;Yuta Yamato;S. Kajihara;P. Girard;Laung-Terng Wang;M. Tehranipoor
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文献类型：
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作者：
H. Furukawa;X. Wen;K. Miyase;Yuta Yamato;S. Kajihara;P. Girard;Laung-Terng Wang;M. Tehranipoor
全速扫描测试易受因过度启动切换活动引起的电源噪声而导致的成品率损失风险的影响。本文提出了一种新的两阶段的计划，即CTX（基于时钟门控的测试松弛和X填充），以减少开关活动时，测试刺激发射。进行测试放松和X填充是为了（1）通过禁用第一阶段（时钟禁用）中时钟门控电路的相应时钟控制信号，使尽可能多的FF处于非活动状态，以及（2）使尽可能多的剩余活动FF在第二阶段（FF-静音）中具有相等的输入和输出值。CTX有效地减少了发射切换活动，从而产生损失风险，即使在测试压缩中使用少量的donpsilat care（X）位，也不会对测试数据量、故障覆盖率、性能和电路设计产生任何影响。
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.