Background calibration techniques for multistage pipelined ADCs with digital redundancy
Background calibration techniques for multistage pipelined ADCs with digital redundancy
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DOI：
10.1109/tcsii.2003.816921
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发表时间：
2003-09-01
期刊：
影响因子：
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通讯作者：
Moon, UK
中科院分区：
文献类型：
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作者：
Li, JP;Moon, UK
建议的数字背景校准方案，适用于多级（流水线或算法/循环）的模数转换器（ADC），纠正电容失配和有限的运算放大器增益造成的线性误差。高精度校准是通过基于每一级的等效基数重新计算数字输出来实现的。利用数字相关法在背景中提取等效根。所提出的校准技术利用了大多数流水线ADC固有的数字冗余架构。在所提出的方法中，信噪比不会从伪随机噪声序列注入到系统中降级。提出了一种开销可忽略的双通道ADC结构，以显著提高数字相关的效率。仿真结果证实，在sigma = 0.1%电容失配和60 dB运放增益下，ADC校准后可实现16位线性度。
The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage's equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with sigma = 0.1% capacitor mismatches and 60 dB opamp gain.