Simplified Josephson-junction fabrication process for reproducibly high-performance superconducting qubits
Simplified Josephson-junction fabrication process for reproducibly high-performance superconducting qubits
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DOI:
10.1063/5.0037093
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发表时间:
2021-02-08
影响因子:
4
通讯作者:
Roudsari, A. Fadavi
中科院分区:
文献类型:
--
作者:
Osman, A.;Simon, J.;Roudsari, A. Fadavi
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T-1 relaxation times averaging above50mu s (Q > 1.5 x 106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty0.5 x 0.5-cm(2) chips, with junction areas ranging between 0.01 and 0.16 mu m(2). The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%-2.5%. We show that 60%-70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.