Variation-aware layout-driven scheduling for performance yield optimization
Variation-aware layout-driven scheduling for performance yield optimization
复制标题
用于性能产量优化的变化感知布局驱动调度
DOI：
10.1109/iccad.2010.5654344
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Deming Chen
中科院分区：
文献类型：
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作者：
Gregory Lucas;Deming Chen
随着向深亚微米工艺的发展，基于RTL的设计方法的设计生产率差距继续扩大。高级综合被吹捧为设计生产力差距的解决方案，它允许设计人员进入更高的抽象层次，专注于电路的功能而不是低层次的细节。然而，与此同时，向深亚微米工艺的转变导致工艺变化水平的增加，这在合成期间必须被考虑，以便电路的性能良率满足设计规格。在本文中，我们解决的问题，性能成品率优化调度任务的高级综合。我们制定的问题的性能产量优化调度作为一个整数线性规划问题（ILP），并提供了以下贡献：1）一个完全么模ILP制定性能产量最大化和2）的变化感知和布局驱动的迭代算法的性能产量的改善。实验结果表明，我们可以获得显着的增益相比，一个国家的最先进的变化感知的高级综合工具快速产量的性能产量。
With the move to deep submicron processes, the design-productivity gap has continued to widen for RTL-based design methodologies. High-level synthesis has been touted as a solution to the design-productivity gap by allowing designers to move up to a higher level of abstraction where they focus on the functionality of the circuit instead of the low level details. However, at the same time, the move to deep submicron processes has led to increased levels of process variation, which must be considered during synthesis so that the performance yield of the circuit meets design specifications. In this paper, we tackle the problem of performance yield optimization during the scheduling task of high-level synthesis. We formulate the problem of performance yield optimization for scheduling as an integer linear programming problem (ILP) and offer the following contributions: 1) a totally unimodular ILP formulation for performance yield maximization and 2) a variation-aware and layout-driven iterative algorithm for performance yield improvement. Experimental results show that we can obtain significant gain in performance yield compared to a state-of-the-art variation-aware high-level synthesis tool Fast Yield.