Efficient and Fast Hardware Architectures for SIKE Round 2 on FPGA
Efficient and Fast Hardware Architectures for SIKE Round 2 on FPGA
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FPGA 上 SIKE Round 2 高效、快速的硬件架构
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Mehran Mozaffari Kermani
中科院分区：
文献类型：
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作者：
Rami Elkhatib;R. Azarderakhsh;Mehran Mozaffari Kermani
.在进一步的密码分析研究表明所选初始素数的安全级别被高估后，在NIST第二轮标准化过程中提出了新的素数用于超奇异同构密钥封装（SIKE）[1，3]。在本文中，我们开发了一种高度优化的F p蒙哥马利乘法算法和架构，与文献中以前的实现相比，该算法和架构进一步利用了SIKE素数的特殊形式。然后，我们使用建议的乘法器在Xilinx Virtex 7上实现了所有第2轮NIST安全级别的SIKE（NIST安全级别1的SIKep434，NIST安全级别2的SIKep503，NIST安全级别3的SIKep610和NIST安全级别5的SIKep751）。我们最好的实现（NIST安全级别1）运行速度快29%，占用硬件资源少30%，与文献[13]中的领先同行相比，其他安全级别的实现也取得了类似的改进。
. New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were over-estimated [1,3]. In this paper, we develop a highly optimized F p Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We then implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 29% faster and occupies 30% less hardware resources in comparison to the leading counterpart available in the literature [13] and implementations for other security levels achieved similar improvement.
后量子密码学蒙哥马利乘法的优化算法和架构
DOI：
10.1007/978-3-030-31578-8_5
发表时间：
2019
期刊：
International Conference on Cryptology and Network Security CANS 2019
影响因子：
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作者：
El Khatib, Rami;Azarderakhsh, Reza;Mozaffari-Kermani, Mehran
通讯作者：
Mozaffari-Kermani, Mehran