A large-signal equivalent circuit model for substrate-induced drain-lag phenomena in HJFETs
A large-signal equivalent circuit model for substrate-induced drain-lag phenomena in HJFETs
复制标题
HJFET 中衬底引起的漏极滞后现象的大信号等效电路模型
DOI：
10.1109/16.535316
复制
发表时间：
1996
影响因子：
3.1
通讯作者：
Y. Ohno
中科院分区：
文献类型：
--
作者：
K. Kunihiro;Y. Ohno
针对沟道深陷引起的漏滞后现象，建立了一个大信号HJFET模型。该模型基于自反门限和Shockley-Read-Hall(SRH)统计。二维器件模拟表明，在大信号条件下，深陷阱中的电子捕获比电子发射快得多，因此漏电流对外加电压的上升和下降阶跃表现出不同的响应。在电路模型中，深陷阱中的电子捕获和发射用由二极管和电阻组成的并联电路来表示，这是从SRH统计中物理推导出来的。该模型与二维仿真结果和大信号电压阶跃下的实验电流暂态数据吻合较好。此外，该模型准确地描述了小信号漏电导色散和温度对陷阱现象的影响。
A large-signal HJFET model is developed for drain-lag phenomena caused by deep traps beneath the channel. The model is based on the self-backgating and Shockley-Read-Hall (SRH) statistics. It is shown by two-dimensional (2D) device simulation that electron capture in deep traps is much faster than electron emission under large-signal conditions; therefore, drain current exhibits different responses for rising and falling steps of applied voltage. In the circuit model, electron capture and emission in deep traps are expressed by a parallel circuit consisting of a diode and a resistor, which are physically deduced from SRH statistics. The model agrees well with the 2D simulation results and experimental current-transient data for large-signal voltage steps. In addition, this model accurately describes small-signal drain-conductance dispersion and temperature effects on the trapping phenomena.