A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation
复制标题
具有子栅极延迟 TDC、相位插值分频器和数字失配消除功能的 3MHz-BW 3.6GHz 数字分数 N PLL
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
A. Lacaita
中科院分区：
文献类型：
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作者：
Marco Zanuso;S. Levantino;C. Samori;A. Lacaita
Digital Fractional-N PLLs allows easy cancellation of ΔΣ quantization noise and spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional-N synthesizer, which combines a 4ps TDC with digital linearization algorithm and a feedback phase interpolator with mismatch cancellation algorithm. In contrast to other TDC linearization approaches [3], this structure allows multiplier-free computations, fast and accurate spur cancellation, as well as digital post-cancellation of phase errors induced by the phase interpolator mismatches, avoiding more complex calibration loops [4].
