50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS
50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS
复制标题
DOI：
10.1109/isscc.2009.4977468
复制
发表时间：
2009-05
期刊：
影响因子：
--
通讯作者：
K. Raczkowski;S. Thijs;W. Raedt;B. Nauwelaers;P. Wambacq
中科院分区：
文献类型：
--
作者：
K. Raczkowski;S. Thijs;W. Raedt;B. Nauwelaers;P. Wambacq
近年来的研究表明，缩小规模的CMOS是实现60 GHz左右高数据速率无线通信收发器的重要候选技术[1，2]。一种低成本的实现方式是将数字部分与收发器结合到单个芯片上。数字部分的复杂性要求非常先进的CMOS技术，例如45 nm低功耗（LP）CMOS。虽然该技术具有高于200 GHz的高最大可编程温度，但后端工艺（BEOL）金属化层比不太先进的技术更薄。这意味着无源元件的品质因数较低，并且由于金属层的薄层电阻较高而导致固有ESD鲁棒性较低。这些限制以及CMOS有限的功率能力使得毫米波功率放大器（PA）的设计更具挑战性[3，4]。
Research in recent years has shown that downscaled CMOS is a serious technology candidate to implement transceivers for high-data-rate wireless communication around 60GHz [1,2]. A low-cost implementation is the combination of the digital part with the transceiver onto a single chip. The complexity of the digital part demands a very advanced CMOS technology, such as 45nm low-power (LP) CMOS. Although this technology features a high maximum ƒT, above 200GHz, the back-end-of-line (BEOL) metallization layers are thinner than in less-advanced technology. This implies a lower quality factor for the passive components and a lower intrinsic ESD robustness due to a higher sheet resistance of the metal layers. These restrictions, together with the limited power capabilities of CMOS make the design of mm-wave power amplifiers (PAs) more challenging [3,4].