Design of an extended 2D mesh network-on-chip and development of A fault-tolerant routing method
Design of an extended 2D mesh network-on-chip and development of A fault-tolerant routing method
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DOI：
10.1049/iet-cdt.2018.5032
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发表时间：
2019-01
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通讯作者：
Yota Kurokawa;Masaru Fukushi
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文献类型：
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作者：
Yota Kurokawa;Masaru Fukushi
本文提出了一种扩展的二维网状片上网络架构，用于基于区域的容错路由方法。所提出的架构在网状网络的四个侧面具有额外的链路和交换机轨道，以便它可以部分地重新配置故障区域周围的网络，以提供新的迂回路径。这允许简化现有容错路由方法的复杂路由规则，并避免长迂回路由路径。提出了一种改进的路由方法，并证明了该结构的无死锁性。仿真结果表明，所提出的架构与修改后的路由方法减少了约39%的平均通信延迟相比，现有的国家的最先进的方法，在牺牲低的硬件开销。
This paper proposes an extended two-dimensional mesh Network-on-Chip architecture for region-based fault tolerant routing methods. The proposed architecture has an additional track of links and switches at the four sides of a mesh network so that it can partially reconfigure the network around faulty regions to provide new detour paths. This allows to simplify the complex routing rules of the existing fault-tolerant routing methods and avoid long detour routing paths. Modified routing method is also proposed for the new architecture and the deadlock freeness is proved. Simulation results show that the proposed architecture with the modified routing method reduces the average communication latency by about 39% compared to the existing state-of-the-art method at the expense of low hardware overhead.