A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing
A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing
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DOI：
10.1109/tcsi.2008.926983
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发表时间：
2009-01-01
影响因子：
5.1
通讯作者：
Shibata, Tadashi
中科院分区：
文献类型：
--
作者：
Ito, Kiyoto;Tongprasit, Benjamas;Shibata, Tadashi
在本文中，开发了一种配备片上图像处理能力的计算数字像素传感器（DPS）。为了解决传感器阵列和片上处理单元之间的互连瓶颈，提出了一种新的块读出架构并在芯片上实现。来自传感器阵列的数据以与内核图像处理兼容的像素块的形式读出，并由片上处理单元并行处理。这样的架构使我们能够使用单指令多数据处理单元的线性阵列来执行高效的内核处理。为了展示这种架构的优势，在芯片上实现了排序滤波电路作为片上图像处理的案例研究。在本文中，在简单的电路中实现了二分搜索排序过滤算法。采用 0.35μm CMOS 技术设计和制造了具有 64x48 像素阵列的概念验证芯片，并且该概念已通过制造芯片的测量得到验证。
In this paper, a computational digital pixel sensor (DPS) equipped with an on-chip image-processing capability has been developed. In order to resolve the interconnection bottleneck between the sensor array and on-chip processing units, a new block-readout architecture has been proposed and implemented on the chip. The data from the sensor array are read out in a form of a pixel block compatible to kernel image processing, and they are processed in parallel by on-chip processing units. Such an architecture has enabled us to carry out an efficient kernel processing using a linear array of single-instruction-multiple-data processing units. In order to demonstrate the advantage of such an architecture, a rank-order filtering circuit has been implemented on the chip as a case study of the on-chip image processing. In this paper, a binary-search rank-order filtering algorithm has been implemented in a simple circuitry. A proof-of-concept chip having an array of 64x48 pixels was designed and fabricated using a 0.35-mu m CMOS technology, and the concept has been verified by the measurement of fabricated chips.