Design and Evaluation of a Configurable Query Processing Hardware for Data Streams

Design and Evaluation of a Configurable Query Processing Hardware for Data Streams
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DOI:
10.1587/transinf.2015edp7203
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发表时间:
2015-12
期刊:
IEICE Trans. Inf. Syst.
影响因子:
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通讯作者:
Yasin Oge;Masato Yoshimi;T. Miyoshi;H. Kawashima;H. Irie;T. Yoshinaga
Yasin Oge;Masato Yoshimi;T. Miyoshi;H. Kawashima;H. Irie;T. Yoshinaga
中科院分区:
其他
文献类型:
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作者:
Yasin Oge;Masato Yoshimi;T. Miyoshi;H. Kawashima;H. Irie;T. Yoshinaga

文献摘要

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总结本文,我们提出了可配置的查询处理硬件(CQPH),这是一种基于FPGA的加速器,用于通过数据流进行连续查询处理。 CQPH是一种高度优化和最小的执行引擎,旨在为高量数据流提供实时响应。与大多数基于FPGA的大多数方法不同,CQPH使用其自身的动态配置机制为多个查询提供了即时的配置性。使用专用查询编译器,可以在运行时轻松地将SQLLIKE查询配置为CQPH。 CQPH支持连续查询,包括选择,小组操作和滑动窗口聚合,并具有大量重叠的滑动窗口。作为概念证明,在FPGA平台上实现了CQPH的原型,以进行案例研究。评估结果表明,给定的查询只能在几微秒内配置,并且CQPH的原型实现每秒可以处理超过1.5亿个元组,而延迟小于微秒。结果还表明,CQPH提供了线性可伸缩性,以提高其灵活性(即,可以配置性),而无需牺牲性能(即最大允许时钟速度)。
SUMMARY In this paper, we propose Configurable Query Processing Hardware (CQPH), an FPGA-based accelerator for continuous query processing over data streams. CQPH is a highly optimized and minimaloverhead execution engine designed to deliver real-time response for highvolume data streams. Unlike most of the other FPGA-based approaches, CQPH provides on-the-fly configurability for multiple queries with its own dynamic configuration mechanism. With a dedicated query compiler, SQLlike queries can be easily configured into CQPH at run time. CQPH supports continuous queries including selection, group-by operation and sliding-window aggregation with a large number of overlapping sliding windows. As a proof of concept, a prototype of CQPH is implemented on an FPGA platform for a case study. Evaluation results indicate that a given query can be configured within just a few microseconds, and the prototype implementation of CQPH can process over 150 million tuples per second with a latency of less than a microsecond. Results also indicate that CQPH provides linear scalability to increase its flexibility (i.e., on-the-fly configurability) without sacrificing performance (i.e., maximum allowable clock speed).