PCB pin-field considerations for 40 Gb/s SerDes channels
PCB pin-field considerations for 40 Gb/s SerDes channels
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40 Gb/s SerDes 通道的 PCB 引脚字段注意事项
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
E. Daniel
中科院分区：
文献类型：
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作者：
M. Degerstrom;D. Post;B. Gilbert;E. Daniel
对于新兴的 40 Gb/s 电气 SerDes 链路而言，设计引脚区和相关结构将具有挑战性。目前尚不清楚传统印刷电路板 (PCB) 技术中实现的引脚区域是否能够支持这些高数据速率。我们通过建模和测量证明，只要设计谨慎，PCB 引脚域对于高达 40 Gb/s 的数据速率似乎是可行的。
Designing pin-fields and related structures will be challenging for emerging 40 Gb/s electrically-based SerDes links. It is not known whether pin-fields implemented in conventional printed circuit board (PCB) technology will be capable of supporting these high data rates. We demonstrate through modeling and measurements that PCB pin-fields appear viable for data rates up to 40 Gb/s, provided that care is taken in the design.