An Area-efficient Unified Transform Architecture for VVC
An Area-efficient Unified Transform Architecture for VVC
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DOI：
10.1109/iscas48785.2022.9937709
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发表时间：
2022-05
期刊：
影响因子：
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通讯作者：
Zhijian Hao;Qi Zheng;Yibo Fan;Guoqing Xiang;Peng Zhang;Heming Sun
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文献类型：
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作者：
Zhijian Hao;Qi Zheng;Yibo Fan;Guoqing Xiang;Peng Zhang;Heming Sun
下一代视频编码标准通用视频编码(VVC)对变换模块采用多重变换选择(MTS)，以较高的计算复杂度为代价提高了编码效率。与高效视频编码(HEVC)相比，VVC支持更大的尺寸，并将变换类型扩展到离散余弦变换(DCT)-II、离散正弦变换(DST)-VII和DCT-VIII。提出了一种区域高效的VVC统一体系结构。为了减少面积消耗，我们提出了一种通用变换的优化计算方案，将变换矩阵分解成两个更简单的矩阵，即低值矩阵和误差矩阵。在分解算法的基础上，设计了基于移位加法单元(SAU)的矩阵乘法电路，可实现三种类型的可复用。因此，此统一架构能够在VVC中执行所有类型和规模。综合结果表明，与相关的32点变换相比，该结构的面积减少了37.9%和72.2%。
The next-generation video coding standard Versatile Video Coding (VVC) adopts Multiple Transform Selection (MTS) to the transform module, improving coding efficiency at the expense of high computational complexity. Compared to High Efficiency Video Coding (HEVC), VVC supports larger sizes and extends the transform types to Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII, and DCT-VIII. This paper presents an area-efficient unified architecture for VVC. To reduce the area consumption, we propose an optimized calculation scheme for general transformations where the transform matrix is decomposed into two simpler matrices named the Low-value matrix and the Error matrix. Based on the decomposition algorithm, Shift-Addition Units (SAUs)-based circuits are designed to conduct matrix multiplication and can be reused by three types. As a result, this unified architecture is capable of performing all types and sizes in VVC. The synthesis results indicate that this architecture achieves an area reduction of 37.9% $\sim$ 72.2% compared with related works for 32-point transforms.