Design and analysis of digital data recovery circuits using oversampling
Design and analysis of digital data recovery circuits using oversampling
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DOI：
10.1049/iet-cds:20045173
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发表时间：
2007-03
期刊：
影响因子：
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通讯作者：
S. Jou;Chih-Hsien Lin;Yen-Hung Chen;Zheng-Hong Li
中科院分区：
文献类型：
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作者：
S. Jou;Chih-Hsien Lin;Yen-Hung Chen;Zheng-Hong Li
提出了一种基于过采样方法的全数字数据恢复的性能评估和电路结构。该架构非常规则，因此非常适合标准单元实现流程。由于其前馈结构，所需的比特率可以通过适当的流水线来实现。这些特性使得所提出的架构非常适合作为软硅知识产权。分析了过采样技术中数据抖动、时钟抖动和过采样率等关键设计参数的综合影响对误码率的影响。因此，不同规格的数据恢复可以设计不同的设计参数。建立了一个能自动估计设计参数的模块生成器。设计实现表明，在0.25 μ m2.5VCMOS工艺标准单元设计下，所提出的全数字数据恢复电路可以达到3.07Gbit/s（布局后），芯片面积为380×390 μm2。
A performance evaluation and circuit architecture for all-digital data recovery using an oversampling method is proposed. The architecture is very regular and hence very suitable for standard-cell implementation flow. Due to its feedforward architecture, the required bit-rate can be achieved through proper pipelining. These properties make the proposed architecture very suitable as soft silicon intellectual property. Analysis of BER due to the combined effects of the key design parameters like data jitter, clock jitter and oversampling ratio in the oversampling technique are carried out. Thus different specifications of data recovery can be designed with different design parameters. A module generator that can estimate the design parameters automatically is established. Design implementation shows the proposed all-digital data recovery circuit can achieve 3.07 Gbit/s (post-layout) with 0.25 µm 2.5 V CMOS technology standard-cell design and occupies 380×390 µm2 chip area.