Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding
Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding
复制标题
用于位串行 LDPC 解码的低复杂度前两个最小值生成器
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
M. Sunwoo
中科院分区：
文献类型：
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作者：
J. Lee;M. Sunwoo
本文提出了一种用于位串行方案的低复杂度的首两个最小值生成器。由于生成器的硬件复杂性占用了最小和低密度奇偶校验解码器的很大一部分，因此低复杂度生成器至关重要。为了降低硬件复杂度，提出了一种现有的位串行发生器，它只找到一个最小值而不是两个最小值；然而，它会导致误码率（BER）下降。相比之下，所提出的低复杂度位序列发生器可以精确地找到前两个最小值，从而提高了误码率性能。此外，提议的生成器不会遭受任何吞吐量损失，因为它的延迟几乎与现有生成器相同。
This brief proposes a low-complexity first-two-minimum-values generator for a bit-serial scheme. Since the hardware complexity of generators utilizes a significant portion of the min-sum low-density parity-check decoder, a low-complexity generator is crucially important. To reduce hardware complexity, an existing bit-serial generator that finds only one minimum value instead of two has been proposed; however, it can cause bit error rate (BER) degradation. By contrast, the proposed low-complexity bit-serial generator can find the exact first two minimum values and thus can improve the BER performance. Moreover, the proposed generator does not suffer from any throughput loss since its latency is almost the same as that of the existing generator.