K-T. Park, T. Nakamura, K-W. Lee, H. Kurino, M. Koyanagi, et al.: "A WAFER-LEVEL THREE DIMENSIONAL CHIP STACKING TECHNOLOGY FOR HIGH-PERFORMANCE MICROELECTRONICS AND MEMS"Proc. of IPACK'01 The Pacific Rim/ASME Int. Electronic Packaging Technical Conferenc
K-T. Park, T. Nakamura, K-W. Lee, H. Kurino, M. Koyanagi, et al.: "A WAFER-LEVEL THREE DIMENSIONAL CHIP STACKING TECHNOLOGY FOR HIGH-PERFORMANCE MICROELECTRONICS AND MEMS"Proc. of IPACK'01 The Pacific Rim/ASME Int. Electronic Packaging Technical Conferenc
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