Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
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可变延迟加法器（VL-adder）：克服NBTI的新算术电路设计实践
DOI：
10.1145/1283780.1283822
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
Cheng
中科院分区：
文献类型：
--
作者：
Yiran Chen;Hai Helen Li;Jing Li;Cheng
负偏压温度不稳定性(NBTI)已成为纳米PMOS晶体管的主要可靠性问题。本文提出了一种用于NBTI容错的可变延迟加法器(VL-ADDER)技术。通过实时检测电路故障，该VL加法器能够自动移位捕获时钟边沿的数据，以容忍关键时序路径上NBTI引起的延迟退化。VL加法器在固定的电源电压和时钟周期下工作，避免了现有NBTI容限技术带来的高设计和制造成本。与其他相关的低功耗加法器设计相比，VL加法器技术在整个芯片生命周期内始终提供更高的能效，而性能降幅非常有限(4.6%或更低)。
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift data capturing clock edge to tolerate NBTI-induced delay degradation on critical timing paths. VL-adder operates with a fixed supply voltage and clock period, avoiding the high design and manufacturing costs incurred by existing NBTI-tolerant techniques. Compared to other related lower-power adder designs, VL-adder technique always provides better energy efficiency through the whole chip lifetime with very limited performance degradation (4.6% or less).