A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA
A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA
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一种节能可重构加速器CMA的硬件完整检测机制
DOI：
10.1109/fpl.2013.6645594
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
H. Amano
中科院分区：
文献类型：
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作者：
Akihito Tsusaka;Mai Izawa;Rie Uno;Nobuyuki Ozaki;H. Amano
Cool Mega Array （CMA）是一种节能的粗粒度可重构处理器阵列（CGRA），由一个大型PE （Processing Element）阵列组成。为了减少存储中间结果和时钟树的功耗，PE阵列采用组合电路构成。提出了一种CMA硬件完成检测机制，并对其进行了实现和评估。每个PE使用具有可选抽头的串行连接缓冲器，延迟根据PE中执行的操作来决定。由于完成信号完全在与计算相同的路径上传输，因此考虑了开关和电线的延迟。后布局仿真表明，在没有该机制的情况下，仅以5.1%的面积开销和不到6%的额外功耗即可获得相同的性能。利用该机制，单个微码可用于PE阵列的各种电源电压。
Cool Mega Array (CMA) is an energy efficient Coarse Grained Reconfigurable processor Array (CGRA) consisting of a large PE (Processing Element) array. In order to reduce the power for storing intermediate results and clock tree, the PE array is consisting of combinatorial circuits. A hardware completion detection mechanism for CMA is proposed, implemented and evaluated. Each PE uses serially connected buffers with selectable taps, and the delay is decided according to the operation executed in the PE. Since the completion signal is transferred exactly on the same paths that for computation, the delay in the switch and wires are accounted. The post layout simulation revealed that the same performance without the mechanism can be obtained only with 5.1% area overhead and less than 6% extra power consumption. With the mechanism, a single micro-code can be used for various supply voltages to PE array.