Systolic computational memory approach to high-speed codebook design
Systolic computational memory approach to high-speed codebook design
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DOI：
10.1109/isspit.2005.1577119
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
K. Sano;C. Takagi;T. Nakamura
中科院分区：
文献类型：
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作者：
K. Sano;C. Takagi;T. Nakamura
本文提出了一种用于矢量量化（VQ）所需的高速码书设计的脉动计算存储器方法。我们提出的脉动计算存储器具有脉动阵列和计算RAM的优点：大规模并行处理能力和宽带宽的内部存储器。通过引入延迟更新的码本，最小最大部分失真竞争学习（MMPDCL）算法的并行性增强，并充分利用所提出的脉动计算存储器的高速码本设计。基于矢量量化的图像压缩实验表明，在33 MHz的频率下，基于FPGA的原型码书设计速度比在2 GHz的通用微处理器上的软件方法快400倍左右
This paper presents a systolic computational memory approach to high-speed codebook design required for vector quantization (VQ). Our proposed systolic computational memory has the advantages of both the systolic array and computational RAM: massively parallel processing capability and wide bandwidth of internal memory. By introducing deferred update of a codebook, the parallelism of the mini-max partial distortion competitive learning (MMPDCL) algorithm is enhanced and fully exploited by the proposed systolic computational memory for high-speed codebook design. The experiments of VQ-based image compression show that the FPGA-based prototype running at 33 MHz achieves about 400 times faster codebook design than a software approach on a general-purpose microprocessor running at 2 GHz