Neural Spike Sorting Using Binarized Neural Networks
Neural Spike Sorting Using Binarized Neural Networks
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DOI：
10.1109/tnsre.2020.3043403
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发表时间：
2020-12
影响因子：
4.9
通讯作者：
D. Valencia;A. Alimohammad
中科院分区：
文献类型：
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作者：
D. Valencia;A. Alimohammad
本文介绍了用于脑植入神经尖峰分类的二元化神经网络（BNN）的设计和有效的硬件实现。与传统的人工神经网络（ANN）相反，使用真实值表示神经元的权重和激活函数，BNNS利用二氧化重量和激活函数大大降低了ANN的记忆要求和计算复杂性。设计的BNN使用几个逼真的神经数据集进行了训练，以验证其神经尖峰分类的准确性。在标准的0.18- $ \ MU \文本{M} $ CMOS进程中，设计BNN的特定于应用集成电路（ASIC）实现占硅面积0.33 mm 2。 ASIC布局的功耗估计表明，BNN在24 kHz运行时从1.8 V电源中消散了$ 2.02〜 \ Mu \ text {w} $。设计基于BNN的SPIKE分选系统还可以在现场可编程的门阵列上实现，并且与替代性最先进的Spike分类系统相比，可将所需的片上存储器减少89％。据我们所知，这是使用BNN进行实时在体内神经尖峰分类中的第一项工作。
This article presents the design and efficient hardware implementation of binarized neural networks (BNNs) for brain-implantable neural spike sorting. In contrast to the conventional artificial neural networks (ANNs), in which the weights and activation functions of neurons are represented using real values, the BNNs utilize binarized weights and activation functions to dramatically reduce the memory requirement and computational complexity of the ANNs. The designed BNN is trained using several realistic neural datasets to verify its accuracy for neural spike sorting. The application-specific integrated circuit (ASIC) implementation of the designed BNN in a standard 0.18- $\mu \text{m}$ CMOS process occupies 0.33 mm 2 of silicon area. Power consumption estimation of the ASIC layout shows that the BNN dissipates $2.02~\mu \text{W}$ of power from a 1.8 V supply while operating at 24 kHz. The designed BNN-based spike sorting system is also implemented on a field-programmable gate array and is shown to reduce the required on-chip memory by 89% compared to those of the alternative state-of-the-art spike sorting systems. To the best of our knowledge, this is the first work employing BNNs for real-time in vivo neural spike sorting.