Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher
复制标题
针对 Serpent 分组密码的位片实现的泄漏功率分析攻击
DOI：
10.1109/mixdes.2014.6872193
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
A. Trifiletti
中科院分区：
文献类型：
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作者：
M. Alioto;Simone Bongiovanni;G. Scotti;A. Trifiletti
在这项工作中的有效性泄漏功率分析（LPA），一类新的侧信道攻击密码电路，已被证明的案例研究。LPA攻击已经针对Serpent块密码的位片实现进行了安装。在测量了处理器内部的位片单元的泄漏贡献之后，选择该位片单元作为LPA攻击的选择函数，已经识别出适当的功率模型。为了考虑由于处理器内部其他逻辑的静态消耗而引起的片上噪声，根据等效门的计数来估计SNR。位片子块采用65纳米CMOS技术节点设计，适用于不同的逻辑风格，即CMOS、WDDL、MDPL和SABL。仿真结果表明，对于每个逻辑实现的算法的正确的关键已经恢复了最多50.000测量，表明LPA攻击可以成功地进行了广泛的逻辑风格，即使他们有效地挫败了标准的DPA和CPA攻击。静态功率预计将成为更大的缩小技术，因此LPA必须被视为一个严重的威胁，密码VLSI电路的安全性。
In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-channel attacks against cryptographic circuits, has been demonstrated on a case study. LPA attacks have been mounted against a bit slice implementation of the Serpent block cipher. After having measured the leakage contribution of a bit slice unit inside the processor, chosen as selection function for LPA attacks, an adequate power model has been identified. In order to consider the on-chip noise due to the static consumption of the other logics inside the processor, an estimation of the SNR has been provided according to the count of equivalent gates. The bit slice sub-block has been designed in a 65nm CMOS technology node for different logic styles, i.e. CMOS, WDDL, MDPL, and SABL. Simulations show that for each logic implementation the correct key of the algorithm has been recovered with a maximum of 50.000 measurements, demonstrating that LPA attack can be successfully carried out against a wide range of logic styles, even if they efficiently thwart standard DPA and CPA attacks. Static power is expected to become greater in downscaled technologies, and thus LPA must be considered a serious threat for the security of cryptographic VLSI circuits.