Hardware Acceleration of Large Scale GCN Inference
Hardware Acceleration of Large Scale GCN Inference
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DOI：
10.1109/asap49362.2020.00019
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发表时间：
2020-07
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通讯作者：
Bingyi Zhang;Hanqing Zeng;V. Prasanna
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作者：
Bingyi Zhang;Hanqing Zeng;V. Prasanna
图卷积网络（GCNs）已经成为最先进的深度学习模型，用于图的表示学习。GCN推理的硬件加速面临以下挑战：1)输入图的巨大规模；2)GCN推理由稀疏和密集矩阵运算组成的异构工作负载；3)计算过程中沿边缘的不规则信息传播。为了解决上述挑战，我们提出了算法架构协同优化来加速FPGA上的大规模GCN推理。我们首先执行数据分区，以适应有限的片上内存中的每个分区。然后，我们使用了一种由稀疏化和节点重排序组成的两阶段预处理算法。第一阶段（稀疏化）通过合并共同邻居节点来消除高节点的边缘连接。第二阶段（重新排序）有效地对相邻节点进行分组，以提高片上数据的重用。结合上述算法优化，我们提出了一种通用的FPGA架构来流水线GCN中的两个主要计算内核：聚合和转换。我们设计的灵活的数据路径和任务调度策略支持多种GCN模型，从而实现高吞吐量推理。我们在最先进的FPGA平台上评估我们的设计，使用三个大规模数据集：Flickr， Reddit, Yelp。与最先进的多核和GPU基准相比，我们的设计将吞吐量分别提高了30倍和2倍。
Graph Convolutional Networks (GCNs) have become state-of-the-art deep learning models for representation learning on graphs. Hardware acceleration of GCN inference is challenging due to: 1) massive size of the input graph, 2) heterogeneous workload of the GCN inference that consists of sparse and dense matrix operations, and 3) irregular information propagation along the edges during the computation. To address the above challenges, we propose the algorithm-architecture co-optimization to accelerate large-scale GCN inference on FPGA. We first perform data partitioning to fit each partition in the limited on-chip memory. Then, we use a two-phase preprocessing algorithm consisting of sparsification and node reordering. The first phase (sparsification) eliminates edge connections of high-degree nodes by merging common neighbor nodes. The second phase (re-ordering) effectively groups adjacent nodes to improve on-chip data reuse. Incorporating the above algorithmic optimizations, we propose a generic FPGA architecture to pipeline the two major computational kernels in GCN: aggregation and transformation. The flexible data path and task scheduling strategy of our design support various GCN models and lead to high throughput inference. We evaluate our design on state-of-the-art FPGA platform using three large scale datasets: Flickr, Reddit, Yelp. Compared with the state-of-the-art multi-core and GPU baselines, our design improves the throughput by up to $30 \times$ and $2 \times$ respectively.