A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application
A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application
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DOI：
10.1142/s0218126619501081
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发表时间：
2019-06
期刊：
影响因子：
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通讯作者：
Pritam Bhattacharjee;A. Majumder
中科院分区：
文献类型：
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作者：
Pritam Bhattacharjee;A. Majumder
随着移动的计算和通信技术的发展，电池的使用寿命越来越长，这就要求采用低功耗的设计方法。在本文中，我们提出了一种新的低功耗8T触发器（FF）的架构，它已经超过了现有的著名的动态，半动态和显式脉冲触发器的功耗和延迟。这种架构的主要成分是一个电压保持器，它被纳入实现可靠的逻辑开关在设计的传播节点。然而，我们也提出了两种新的门控时钟产生的方法，基于传输门（TG）和传输晶体管逻辑（PTL）作为基于LECTOR的门控的修改。这些门控逻辑已经证明自己是足够的能力，以减少静态和动态功耗，因此被用于所提出的触发器，以实现进一步降低功率比其nongated对应。在有限状态机中测试了该门控触发器的性能，并将其应用于低功耗串行加法器的设计中。所有模拟均采用65 nm和90 nm CMOS技术进行，电源电压为1.1[公式：见正文]V，时钟频率为6.6[公式：见正文]GHz。门控FF节省52.12%，6.36%和28.18%的平均功耗使用LECTOR，TG和PTL，分别相对于其nongated对应的65纳米技术。在商业化的CMOS代工环境中，门控和非门控设计的性能指标得到了肯定。
Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.