Control Flow Prediction Schemes for Wide-Issue Superscalar Processors
Control Flow Prediction Schemes for Wide-Issue Superscalar Processors
复制标题
广泛问题超标量处理器的控制流预测方案
DOI：
10.1109/71.762815
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
M. Franklin
中科院分区：
文献类型：
--
作者：
S. Dutta;M. Franklin
为了实现高性能，宽问题超标量处理器每个周期必须获取大量指令。条件分支是增加获取带宽的主要障碍，因为它们可能会改变控制流并且非常频繁。为了克服这个问题，这些处理器需要在一个循环中预测多个分支的结果。本文研究了两种控制流预测方案，这两种方案利用单个预测来预测多个分支的有效结果。这些方案不以分支作为预测的基本单位，而是以被执行程序的控制流图的子图作为预测的基本单位，一次预测整个子图的目标，从而允许超标量获取机制在一个循环中经过多个分支。研究的第一种控制流预测方案考虑顺序块状子图，第二种方案考虑树状子图进行控制流预测。这两种方案都进行1 / 4的预测，而不是由分支级预测方案进行1 / 2的预测。使用基于MIPS isa的12路超标量微架构对这两种方案进行了评估。在使用分支级预测的相同微处理器上，有效获取大小分别提高了大约25%和50%。虽然控制流预测方案预测1 / 4的结果，但预测精度没有明显差异。
In order to achieve high performance, wide-issue superscalar processors have to fetch a large number of instructions per cycle. Conditional branches are the primary impediment to increasing the fetch bandwidth because they can potentially alter the flow of control and are very frequent. To overcome this problem, these processors need to predict the outcome of multiple branches in a cycle. This paper investigates two control flow prediction schemes that predict the effective outcome of multiple branches with the help of a single prediction. Instead of considering branches as the basic units of prediction, these schemes consider subgraphs of the control flow graph of the executed program as the basic units of prediction and predict the target of an entire subgraph at a time, thereby allowing the superscalar fetch mechanism to go past multiple branches in a cycle. The first control flow prediction scheme investigated considers sequential block-like subgraphs and the second scheme considers tree-like subgraphs to make the control flow predictions. Both schemes do a 1-out-of-4 prediction as opposed to the 1-out-of-2 prediction done by branch-level prediction schemes. These two schemes are evaluated using a MIPS ISA-based 12-way superscalar microarchitecture. An improvement in effective fetch size of approximately 25 percent and 50 percent, respectively, is observed over identical microprocessors that use branch-level prediction. No appreciable difference in the prediction accuracy was observed, although the control flow prediction schemes predicted 1-out-of-4, outcomes.