Advanced Verification Techniques Based on Learning
Advanced Verification Techniques Based on Learning
复制标题
基于学习的高级验证技术
DOI：
10.1145/217474.217564
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发表时间：
1995
期刊：
影响因子：
--
通讯作者：
M. Fujita
中科院分区：
文献类型：
--
作者：
J. Jain;R. Mukherjee;M. Fujita
设计验证在电路合成过程中提出了一个非常实用的问题。基于学习的验证技术被证明是一个有吸引力的选择，用于验证两个具有简单功能关系的内部门的电路。我们提出了一种验证方法，该方法采用了基于符号操作的学习技术，并且可以更有效地学习间接含义。该方法还可以学习一些有用的功能含义。我们还提出了一个框架，其中间接含义技术与基于OBDD的验证工具集成在一起。我们对某些ISCAS电路以及一些非常硬的工业电路提出了高效的验证结果。
Design verification poses a very practical problem during circuit synthesis. Learning based verification techniques prove to be an attractive option for verifying two circuits with internal gates having simple functional relationships. We present a verification method which employs a learning technique based on symbolic manipulation and which can more efficiently learn indirect implications. The method can also learn some useful functional implications. We also present a framework in which an indirect implication technique is integrated with an OBDD based verification tool. We present highly efficient verification results on some ISCAS circuits as well as on some very hard industrial circuits.