The multicluster architecture: reducing cycle time through partitioning
The multicluster architecture: reducing cycle time through partitioning
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多集群架构:通过分区减少周期时间
DOI:
10.1109/micro.1997.645806
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发表时间:
1997
期刊:
影响因子:
--
通讯作者:
Z. Vranesic
中科院分区:
文献类型:
--
作者:
K. Farkas;P. Chow;N. Jouppi;Z. Vranesic
The multicluster architecture that we introduce offers a decentralized, dynamically scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural registers. The motivation for the multicluster architecture is to reduce the clock cycle time, relative to a single-cluster architecture with the same number of hardware resources, by reducing the size and complexity of components on critical timing paths. Resource partitioning, however, introduces instruction-execution overhead and may reduce the number of concurrently executing instructions. To counter these two negative by-products of partitioning, we developed a static instruction scheduling algorithm. We describe this algorithm, and using trace-driven simulations of SPEC92 benchmarks, evaluate its effectiveness. This evaluation indicates that for the configurations considered the multicluster architecture may have significant performance advantages at feature sizes below 0.35 /spl mu/m, and warrants further investigation.