The impact of delay on the design of branch predictors
The impact of delay on the design of branch predictors
复制标题
延迟对分支预测器设计的影响
DOI：
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复制
发表时间：
2000
期刊：
影响因子：
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通讯作者：
Calvin Lin
中科院分区：
文献类型：
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作者：
Daniel A. Jiménez;S. Keckler;Calvin Lin
现代微处理器采用越来越复杂的分支预测器来实现指令获取带宽，以满足宽乱序执行内核的需要。虽然现有的预测器仍然可以在单个时钟周期内访问，但最近的研究表明，更慢的线路和更快的时钟速率将需要对大型片上结构（如分支预测表）进行多周期访问。因此，未来的分支预测器不仅要考虑面积和准确性，还要考虑延迟。本文探讨了在设计分支预测器时的这些权衡，并表明仅仅提高精度并不能克服更大的预测器结构带来的延迟损失。我们评估了适应延迟的三种方案：缓存方法，覆盖方法和级联前瞻性方法。虽然我们使用通用的分支预测器gshare作为预测组件，但这些方案可以使用大多数类型的预测器来构建。
Modern microprocessors employ increasingly complicated branch predictors to achieve instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While existing predictors can still be accessed in a single clock cycle, recent studies show that slower wires and faster clock rates will require multi-cycle access times to large on-chip structures, such as branch prediction tables. Thus, future branch predictors must consider not only area and accuracy, but also delay. The paper explores these tradeoffs in designing branch predictors and shows that increased accuracy alone cannot overcome the penalties in delay that arise with larger predictor structures. We evaluate three schemes for accommodating delay: a caching approach, an overriding approach, and a cascading lookahead approach. While we use a common branch predictor, gshare, as the prediction component, these schemes can be constructed using most types of predictors.