An FPGA Implementation of Dirty Paper Precoder
An FPGA Implementation of Dirty Paper Precoder
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脏纸预编码器的 FPGA 实现
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
A. Harris
中科院分区：
文献类型：
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作者：
Pankaj Bhagawat;Weihuang Wang;M. Uppal;G. Choi;Zixiang Xiong;M. Yeary;A. Harris
肮脏的纸质代码（DPC）可用于许多通信网络应用程序；广播频道，多源干扰频道和ISI频道列举几个。我们研究了基于嵌套的格子技术实施DPC预编码器的各种实施瓶颈和问题。目的是实现无线LAN/DSL应用程序的预编码器的实际硬件实现。我们描述了Xilinx Virtex 2v8000 FPGA上预编码器的建筑发展过程和实现。据我们所知，这是第一个报告的DPC预制硬件硬件实现。
Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We study various implementation bottlenecks and issues with implementing a DPC pre-coder based on nested trellis technique. The aim is to achieve a practical hardware realization of the precoder for wireless LAN/DSL applications. We describe the architectural development process and realization of the precoder on a Xilinx Virtex 2V8000 FPGA. To the best of our knowledge this is the first reported DPC pre-coder hardware implementation.