Using interaction costs for microarchitectural bottleneck analysis
Using interaction costs for microarchitectural bottleneck analysis
复制标题
使用交互成本进行微架构瓶颈分析
DOI：
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
C. Newburn
中科院分区：
文献类型：
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作者：
Brian A. Fields;Rastislav Bodík;M. Hill;C. Newburn
攻击现代处理器中的瓶颈是困难的，因为许多微体系结构事件彼此重叠。这种并行性使得难以同时：（a）向事件分配成本（例如，两个重叠高速缓存未命中之一）;以及（B）为每个周期分配责任（例如，对于许多重叠资源处于活动状态的周期）。本文介绍了一种新的模型，了解事件成本，以促进处理器的设计和优化。首先，我们观察到机器中的所有东西（指令、硬件结构、事件）只能以两种方式（并行或串行）中的一种进行交互。我们通过定义交互成本来量化这些交互，交互成本可以是零（独立，无交互），正（并行）或负（串行）。其次，我们说明了在处理器设计和优化中使用交互成本的价值。最后，我们提出了性能监测硬件测量的交互成本，是适合现代处理器。
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both: (a) assign a cost to an event (e.g., to one of two overlapping cache misses); and (b) assign blame for each cycle (e.g., for a cycle where many, overlapping resources are active). This paper introduces a new model for understanding event costs to facilitate processor design and optimization. First, we observe that everything in a machine (instructions, hardware structures, events) can interact in only one of two ways (in parallel or serially). We quantify these interactions by defining interaction cost, which can be zero (independent, no interaction), positive (parallel), or negative (serial). Second, we illustrate the value of using interaction costs in processor design and optimization. Finally, we propose performance-monitoring hardware for measuring interaction costs that is suitable for modern processors.