3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS
3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS
复制标题
用于 90 nm CMOS 频率合成的 3 V 20 ps 时间数字转换器
DOI：
--
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
P. Balsara
中科院分区：
文献类型：
--
作者：
R. Staszewski;S. Vemulapalli;P. Vallur;J. Wallberg;P. Balsara
提出并实现了一种用90 nm数字芯片实现的20ps时间数字转换器(TDC)。它用作全兼容全球移动通信系统(GSM)收发器的全数字锁相环中的鉴相器/频率检测器和电荷泵替代品。TDC内核基于伪差分数字架构，使其对NMOS和PMOS晶体管失配不敏感。时间转换分辨率等于反相器传播延迟，这是CMOS中最好的逻辑级再生时序。TDC正在进行自我校准，估计精度优于1%。此外，它还可用作这种大型片上系统中模拟电路的CMOS工艺强度估计器。测量的积分非线性度为0.7个最低有效位。TDC的原始功耗为5.3 mA，使用1.3 V电源进行电源管理时的功耗为1.3 mA。
We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least signinfiant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.