An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart
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14nm FinFET 库中的异步 NoC 路由器：与工业同步对应物的比较
DOI：
10.23919/date.2017.7927084
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
G. Sadowski
中科院分区：
文献类型：
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作者：
Weiwei Jiang;D. Bertozzi;Gabriele Miorandi;S. Nowick;W. Burleson;G. Sadowski
介绍了一种异步高性能低功耗5端口片上网络（NoC）路由器。建议的路由器集成了低延迟输入缓冲器，使用循环FIFO设计，和一个新的端到端的信用为基础的虚拟通道（VC）流控制的复制交换机架构。然后将此异步路由器与AMD同步路由器在实际先进的14 nm FinFET库中进行比较。据我们所知，这是第一次使用已经在几个商业产品中制造的真实的同步路由器基线进行这样的比较。初始合成后的预布局实验表明，异步路由器的主要结果相比，同步路由器。特别是，减少55%的面积和28%的延迟改善观察异步实现。此外，88%和58%的闲置和有功功率的节省，分别获得。
An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained.