Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs
Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs
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基于扫描链的观察点，可实现 FPGA 设计的高效运行时调试和验证
DOI：
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发表时间：
2003
期刊：
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通讯作者：
K. Tomko
中科院分区：
文献类型：
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作者：
A. Tiwari;K. Tomko
本文介绍了一种结构化和区域有效的方法，用于基于FPGA的可重构系统的现场调试。将扫描链插入FPGA上运行的硬件设计中，该设计通过提供手表功能来帮助调试和验证。提出的扫描链技术易于使用，开销非常低。基于扫描链的实现将利用较新的FPGA连接多个LUT并将其配置为Shift寄存器的能力。使用Shift寄存器LUTS提出的硬件调试程序不需要设计设计以更改观察点条件，因此非常快。在本文中，讨论了由于添加基于扫描链的观察点逻辑而产生的顶部的区域，并将其与其他提议的调试技术进行了比较。我们观察到，ITC基准电路的平均面积为46％的平均面积为46％，其表点信号宽度不同。
This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watch-point conditions and thus is very fast. In this paper, the area overhead resulting from addition of a scan-chain based watch-point logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.