Implementation of ladder diagram for programmable controller using FPGA
Implementation of ladder diagram for programmable controller using FPGA
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利用FPGA实现可编程控制器梯形图
DOI：
10.1109/etfa.1999.813150
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
T. Sekiguchi
中科院分区：
文献类型：
--
作者：
I. Miyazawa;T. Nagao;M. Fukagawa;Y. Itoh;T. Mizuya;T. Sekiguchi
顺序控制是制造系统的基本技术。制造设备或系统通常由可编程控制器（PC）控制。为了满足小型化和隐藏信息的要求，我们开发了一种新型的控制器，它是使用现场可编程门阵列（FPGA）作为专用集成电路（ASIC）实现的。在顺序控制领域中广泛使用的编程语言梯形图（LD）也在这样的FPGA上实现。实现的主要瓶颈是如何实现循环扫描，这是PC机的最大特点。我们描述了两种方法来实现循环扫描。一种是利用超高速集成电路（VHSIC）硬件描述语言（VHDL）的时钟事件，另一种是将作为LD自保持电路的线圈转换成适当的VHDL触发器元件。我们还比较了这两种方法，并显示由FPGA实现的新的控制器的好处。
Sequential control is an elementary technology for manufacturing systems. Manufacturing devices or systems are usually controlled by programmable controllers (PCs). In order to satisfy the requirements of downsizing and hidden information, we develop a novel type of controller which is implemented using the field programmable gate array (FPGA) as an application specific integrated circuit (ASIC). The widely used programming language in the area of sequential control, Ladder Diagram (LD), is also implemented on such a FPGA. The main bottleneck of the implementation is how to realize cyclic scan, which is the most significant characteristic of PCs. We describe two methods to implement the cyclic scan. One involves using the clock event of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), and the other is of translating a coil as a self-hold circuit of LD into an appropriate flip-flop element of VHDL. We also compare the two methods and show the benefits of the new controller implemented by FPGA.