A Wideband Doherty Architecture With 36% of Fractional Bandwidth
A Wideband Doherty Architecture With 36% of Fractional Bandwidth
复制标题
DOI：
10.1109/lmwc.2013.2281413
复制
发表时间：
2013-09
影响因子：
3
通讯作者：
L. Piazzon;R. Giofré;P. Colantonio;F. Giannini
中科院分区：
文献类型：
--
作者：
L. Piazzon;R. Giofré;P. Colantonio;F. Giannini
This letter presents the design and characterization of a novel wideband Doherty architecture. Both input splitter and output combiner are realized by means of two-sections branch-line alike couplers. The realized prototype based on commercial GaN active devices shows more than 36% of fractional bandwidth, from 1.67 to 2.41 GHz. In this frequency range, the measured drain efficiency is within 59% and 43% at 6 dB of output power back-off and within 72% and 53% at saturation, with an output power around 41 dBm. More than 47% average efficiency and less than -40 dBc adjacent channel power ratio are measured applying a 20 MHz LTE digitally pre-distorted signal when the average output power is around 4 W.
