The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
复制标题
流水线对现场可编程门阵列每次操作能量的影响
DOI：
10.1007/978-3-540-30117-2_73
复制
发表时间：
2004
期刊：
影响因子：
--
通讯作者：
W. Luk
中科院分区：
文献类型：
--
作者：
S. Wilton;Su;W. Luk
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.
