A Systematic Methodology for Design and Analysis of Approximate Array Multipliers
A Systematic Methodology for Design and Analysis of Approximate Array Multipliers
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近似阵列乘法器设计和分析的系统方法
DOI：
10.1109/apccas.2016.7803973
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
Yuko Hara-Azumi
中科院分区：
文献类型：
--
作者：
Takahiro Yamamoto;Ittetsu Taniguchi;Hiroyuki Tomiyama;Shigeru Yamashita;Yuko Hara-Azumi
近似计算被认为是设计低功耗或低面积数字电路的一种很有前途的方法。本文提出了一种设计和分析近似阵列乘法器的系统方法。我们的方法系统地设计了一系列具有不同面积、延迟和精度特性的近似阵列乘法器，以便LSI设计人员可以选择最适合其应用要求的乘法器。我们的实验探讨了近似乘法器的面积、延迟和精度之间的权衡。
Approximate computing is considered as a promising approach to design of power-or area-efficient digital circuits. This paper proposes a systematic methodology for design and analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay and accuracy of the approximate multipliers.