Multi-core based HEVC hardware decoding system
Multi-core based HEVC hardware decoding system
复制标题
基于多核的HEVC硬件解码系统
DOI：
10.1109/icmew.2014.6890626
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
N. Eum
中科院分区：
文献类型：
--
作者：
Hyunmi Kim;Seunghyun Cho;Kyungjin Byun;N. Eum
在这个演示中，一个可扩展的HEVC硬件解码器被演示用于各种应用，包括UHD。该架构包括用于多核管理的控制逻辑和灵活的环路滤波器，该环路滤波器可以处理图片分区的边界，而无需来自流水线的单独的环路滤波器单元。两级并行处理的方法使解码器的高性能应用的实时操作。在FPGA原型板上的演示表明，所提出的可扩展架构的多核设计实现的效率。估计该系统能够实时解码由HEVC编码的UHD视频。
In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline. Two-level parallel processing approach makes the decoder operate in real-time for high-performance applications. The demonstration on FPGA prototype board shows the efficiency of the proposed scalable architecture achieved by multi-core design. The system is estimated to be able to decode UHD video coded by HEVC in real-time.