9.5 efficient digital quadrature transmitter based on IQ cell sharing
9.5 efficient digital quadrature transmitter based on IQ cell sharing
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9.5 基于IQ单元共享的高效数字正交发射机
DOI：
10.1109/isscc.2015.7062979
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
Bumman Kim
中科院分区：
文献类型：
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作者：
Hadong Jin;Dongsu Kim;Sangsu Jin;Hankyu Lee;Kyunghoon Moon;Huijung Kim;Bumman Kim
随着新的复杂通信标准在不同频段使用不同的调制方法，人们对支持这些标准的软件定义无线电(SDR)收发信机的兴趣越来越大。对于灵活的收发信机来说，数字密集型发射机具有许多优势，受到了广泛的追捧。发射器链的效率强烈依赖于功率放大器，而开关功率放大器，如D类和F功率放大器，由于其高效率而被使用。极性发送器适用于开关操作，受到广泛的关注。然而，L/Q到极的转换需要CORDIC，而且非常复杂。此外，与L/Q信号的带宽相比，极信号具有更大的带宽。相反，不需要CORDIC的正交发射机具有结构简单、计算成本低、功耗低等优点。由于其良好的特性，人们对正交发射机进行了研究。[1]采用基于Gilbert混频器的RFDAC。它工作在电流模式下，输出阻抗随导通单元数量的不同而变化。由于阻抗的变化，很难有高的线性度。在[2]中，输入的数字代码被增量-西格玛调制处理，以获得更小的数字比特和更高的分辨率。然而，调制器会产生量化噪声。在[3-6]中，电压模式发射机与基于开关电容器的功率合成器一起使用。输出阻抗是恒定的，由总电容决定，而不考虑电池的开/关条件。此外，这种结构提供了比以前报道的工作更高的输出功率和效率。[4]采用Delta-Sigma调制与级联PWM相结合的方法来提高线性度。在[5]中，采用了正交结构来消除极点结构的问题。由于传统数字L/QLOS的90°相位差，传统的正交发射机的输出功率比极坐标发射机的输出功率低，当I和Q幅值相等时，输出功率最大降低3dB。
As new complex communication standards employ various modulation methods in various frequency bands, interest in the software-defined radio (SDR) transceiver to support the standards is increasing. For the flexible transceiver, a digital-intensive transmitter has many advantages and has been pursued intensively. The efficiency of the transmitter chain is strongly dependent on the PA, and switching PAs, such as Class-D and F PAs, are used due to their high efficiency. A polar transmitter is suited for the switching operation and receives a large attention. However, a CORDIC is needed for l/Q-to-Polar conversion, and it is very complex. Moreover, the polar signal has a large bandwidth compared to the l/Q signal bandwidth. On the contrary, the quadrature transmitter that does not require the CORDIC, is simple and low computing cost with low power consumption. Due to the favorable characteristics, the quadrature transmitters have been studied. [1] employs an RFDAC based on a Gilbert mixer. It operates in a current mode and the output impedance varies with the number of on-cells. Due to the impedance variation, it is difficult to have a high linearity. In [2], the input digital code is processed by delta-sigma modulation for smaller digital bits and enhanced resolution. However the modulator generates quantization noise. In [3-6], a voltage-mode transmitter is employed with a power combiner based on a switched capacitor. The output impedance is constant, determined by the total capacitance regardless of the on/off cell condition. Moreover, this architecture delivers much higher output power and efficiency than previously reported works. [4] used delta-sigma modulation with cascade PWM to improve linearity. In [5], a quadrature architecture was employed to eliminate the problems of the polar architecture. Due to the 90° phase difference of conventional digital l/Q LOs, the output power of the conventional quadrature transmitter has lower than that of polar, maximum 3dB lower when the magnitude of I and Q are equal.