A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications
A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications
复制标题
适用于 64 GBaud 应用的 2 倍过采样、128 GS/s 5 位闪存 ADC
DOI：
--
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
S. Voinigescu
中科院分区：
文献类型：
--
作者：
Alireza Zandieh;P. Schvan;S. Voinigescu
我们报告了任何半导体技术中最高采样率的单芯片ADC。该电路采用2倍时间交错架构，集成两个采样保持放大器，每个放大器驱动一个以64 GHz反相采样的5位闪存子ADC。两个子ADC的数字输出馈入片内128 GS/s温度计编码DAC，其唯一用途是测试ADC。ADC-DAC组合的性能（包括SFDR和4.1位有效位（最高32 GHz输入信号））在芯片上进行了表征，并包括DAC的影响。ADC的功耗和布局尺寸对于128 GS/s的工作速率至关重要，通过采用新颖的1 mA Cherry-Hooper比较器和具有有源峰化功能的准CML MOS-HBT锁存器，将64个ADC通道的每个通道的尺寸减小到$\mathbf{10}\mu\mathbf{m\ 70}\mu\mathbf{m}$，从而最大限度地降低了功耗和布局尺寸。ADC的总功耗为1.25 W，ADC-DAC芯片的总芯片面积为$\mathbf{1.1}\mathbf{mm}\times\mathbf{1.9}\mathbf{mm}$。
We report the highest sampling-rate single-chip ADC in any semiconductor technology. The circuit uses a 2x time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. The digital outputs of the two sub-ADCs feed an on-die 128-GS/s thermometer-coded DAC whose sole purpose is for testing the ADC. The performance of the ADC-DAC combo, including the SFDR, and the ENOB of 4.1 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128-GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-CML MOS-HBT latches with active peaking, which reduced the footprint of each of the 64 ADC-lanes to $\mathbf{10}\mu\mathbf{m\ 70}\mu\mathbf{m}$. The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is $\mathbf{1.1}\mathbf{mm}\times\mathbf{1.9}\mathbf{mm}$.