Strained Silicon Directly on Insulator N- and P-FET nanowire transistors
Strained Silicon Directly on Insulator N- and P-FET nanowire transistors
复制标题
直接在绝缘体 N- 和 P-FET 纳米线晶体管上施加应变硅
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
M. Vinet
中科院分区：
文献类型：
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作者：
S. Barraud;R. Lavieville;C. Tabone;F. Allain;M. Cassé;M. Samson;V. Maffini;M. Vinet
报道了栅极长度和宽度均可达15 nm的高性能应变绝缘体上硅（sSOI）纳米线晶体管。我们证明了sSOI π-栅极n-FET NWs在I<sub>ON</sub>电流为1410 μA/μm时（当I<sub>OFF</sub> = 70 nA/μm），在V<sub>DD</sub>=0.9V时，具有良好的静电抗阻性（DIBL = 140 mV/V， SS<sub>SAT</sub> = 76 mV/dec）。sSOI衬底用于n- fet的有效性显示，在短栅极长度下，I<sub>ON</sub>改善高达+40%。更一般地，尺寸和方向相关的应变对长通道和短通道π栅极SOI NW晶体管中电子和空穴输运的影响进行了系统的研究。
High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with I<sub>ON</sub> current of 1410 μA/μm (when I<sub>OFF</sub> = 70 nA/μm) at V<sub>DD</sub>=0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SS<sub>SAT</sub> = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an I<sub>ON</sub> improvement up to +40% at short gate lengths. More generally, size- and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.