Analysis and design of low-energy flip-flops
Analysis and design of low-energy flip-flops
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DOI：
10.1109/lpe.2001.945371
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发表时间：
2001-08
期刊：
影响因子：
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通讯作者：
D. Markovic;B. Nikolić;R. Brodersen
中科院分区：
文献类型：
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作者：
D. Markovic;B. Nikolić;R. Brodersen
为具有恒定吞吐量的低能量系统开发了一种选择和优化触发器的方法。讨论了与低能量系统相关的表征指标，提供了对电路和系统级别的时序和能量参数的洞察。晶体管尺寸经过优化，可在限制能耗的情况下实现最小延迟。将该方法应用于不同触发器类型的表征及其在0.25/SPLµ/m CMOS工艺中的比较。传输门主从锁存器对具有最大的内部竞争容限、最低的能量消耗，并且具有可与更快的脉冲触发锁存器相媲美的能量延迟乘积。
Develops a methodology for selecting and optimizing flip-flops for low-energy systems with constant throughput. Characterization metrics, relevant to low-energy systems are discussed, providing insight into timing and energy parameters at both the circuit and system levels. Transistor sizes are optimized for minimal delay under constrained energy consumption. This methodology is applied to characterization of various flip-flop styles and their comparison in 0.25 /spl mu/m CMOS technology under scaled supply voltages. A transmission-gate master-slave latch-pair has the largest internal race margin, lowest energy consumption, and has energy-delay product comparable to much faster pulse-triggered latches.