Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs

Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
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规模化 InGaAs 无植入 NanoMOSFET 的基准测试

DOI:
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发表时间:
2008
影响因子:
3.1
通讯作者:
A. Asenov
A. Asenov
中科院分区:
工程技术2区
文献类型:
--
作者:
K. Kalna;N. Seoane;A. García;I. Thayne;A. Asenov

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利用有限元异质结构蒙特卡罗(MC)和平行三维漂移扩散(D-D)模拟研究了具有In0.75Ga0.25As通道的n型无植入(IF) III-V纳米omosfet的潜在性能。这些器件的栅极长度分别为30nm、20nm和15nm,并与0.3 ga0.7 as沟道IF mosfet的等效栅极长度和最先进的Si TriGate FinFET进行了比较。基准研究是基于MC模拟器对高k栅极电介质中相关δ掺杂异质结构的实验输运数据的仔细校准。在0.8 v电源电压下,30 nm栅极长度的In0.75Ga0.25As沟道IF III-V MOSFET预计提供2880 muA/mum的驱动电流,与等效栅极长度In0.3Ga0.7As沟道IF MOSFET相比,其亚阈值斜率为94.7 mV/dec,而2380 muA/mum。当In0.75Ga0.25As沟道中频晶体管缩放到20nm和15nm栅极长度时,驱动电流分别增加到3520和3605 muA/mum,亚阈值斜率分别为107.8和131.7 mV/dec。采用三维三维三维模拟的方法研究了离散掺杂剂在δ掺杂平面上引起的阈值电压变化。30nm、20nm和15nm栅极长度的In0.7Ga0.25As沟道中频晶体管的阈值电压标准差分别为42,58和61 mV,接近或低于具有等效栅极长度的体硅mosfet。
The potential performance of n-type implant-free (IF) III-V nanoMOSFETs with an In0.75Ga0.25As channel is studied using finite-element heterostructure Monte Carlo (MC) and parallel 3D drift-diffusion (D-D) simulations. These devices, scaled to gate lengths of 30, 20, and 15 nm, are compared with the equivalent gate length In0.3Ga0.7As channel IF MOSFETs and with a state-of-the-art Si TriGate FinFET. The benchmarking study is based on careful calibration of the MC simulator against experimental transport data obtained from relevant delta-doped heterostructures with a high-k gate dielectric. At 0.8-V supply voltage, the 30-nm gate length In0.75Ga0.25As channel IF III-V MOSFET is predicted to deliver a drive current of 2880 muA/mum and to have a subthreshold slope of 94.7 mV/dec compared with 2380 muA/mum for an equivalent gate length In0.3Ga0.7As channel IF MOSFET. When the In0.75Ga0.25As channel IF transistor is scaled to 20- and 15-nm gate lengths, the drive current increases to 3520 and 3605 muA/mum, featuring subthreshold slopes of 107.8 and 131.7 mV/dec, respectively. The threshold voltage variability induced by the discrete dopants in the delta-doped plane is studied using 3-D D-D simulations. The 30-, 20-, and 15-nm gate length In0.7Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58, and 61 mV, respectively, which are close to or lower than those observed in bulk Si MOSFETs with equivalent gate lengths.