Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress

Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress
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DOI:
10.1145/3349567.3351730
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发表时间:
2019-10
期刊:
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion
影响因子:
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通讯作者:
Ruben Vazquez;A. Gordon-Ross;G. Stitt
Ruben Vazquez;A. Gordon-Ross;G. Stitt
中科院分区:
其他
文献类型:
--
作者:
Ruben Vazquez;A. Gordon-Ross;G. Stitt

文献摘要

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在本文中,我们提出了我们的高速缓存配置预测方法卸载到FPGA,以提高性能和硬件开销的减少,同时保持高速缓存配置预测的最佳能源高速缓存配置的指令和数据缓存的应用程序阶段的5%。
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.