Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress
Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress
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DOI:
10.1145/3349567.3351730
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发表时间:
2019-10
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通讯作者:
Ruben Vazquez;A. Gordon-Ross;G. Stitt
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文献类型:
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作者:
Ruben Vazquez;A. Gordon-Ross;G. Stitt
In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.