A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
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适用于超低功耗应用的 45nm CMOS 0.35v 优化标准单元库
DOI：
10.1145/1594233.1594288
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发表时间：
2009
期刊：
影响因子：
--
通讯作者：
G. Sicard
中科院分区：
文献类型：
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作者：
F. Abouzeid;S. Clerc;F. Firmin;M. Renaudin;G. Sicard
超低电压现在是使用纳米工艺技术设计的能源受限应用的众所周知的解决方案。这项工作的重点是建立一种自动化方法，以便仅使用标准 EDA 工具即可设计超低压数字电路。为了实现这一目标，开发了 0.35V 能量延迟优化库。该库完全符合标准库设计流程和特性，并通过 BCH 解码器电路的设计和制造以及标准前端到后端流程进行了验证。它的执行频率为 457 kHz，每个周期的总能耗为 2.9fJ。
Ultra-low voltage is now a well known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting-up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. It performs at 457 kHz, with a total energy consumption of 2.9fJ per cycle.