A 64Kb full CMOS RAM with divided word line structure
A 64Kb full CMOS RAM with divided word line structure
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具有分割字线结构的 64Kb 全 CMOS RAM
DOI：
10.1109/isscc.1983.1156503
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发表时间：
1983
期刊：
影响因子：
--
通讯作者：
T. Nakano
中科院分区：
文献类型：
--
作者：
Masahiko Yoshimoto;K. Anami;Hirofumi Shinohara;Tsutomu Yoshihara;H. Takagi;S. Nagao;S. Kayano;T. Nakano
本文将描述一种8K×8bN-well CMOS静态随机存取存储器，该静态随机存取存储器具有可同时降低列电流和字线延迟的分割字线结构。该RAM实现了50 ns的访问时间，同时功耗为100 mW。综述了硅化钼作为第二层多晶硅的替代物的应用。
An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.