Impact of mutual inductance on timing in nano-scale SoC
Impact of mutual inductance on timing in nano-scale SoC
复制标题
纳米级 SoC 中互感对时序的影响
DOI：
10.1587/elex.15.20180376
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
T. Kanamoto
中科院分区：
文献类型：
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作者：
Kazuyuki Sakata;Takashi Hasegawa;K. Ichikawa;T. Kanamoto
根据纳米级片上系统（SoC）的电阻(R)、电感(L)和电容(C)，研究了互感(M)对互连信号延迟估计的影响，提出了一种预测和抑制这种影响的方法。提出的方法首先计算一组参数变化下RLC和RLMC导线模型之间的延迟差异，然后使用包括导线宽度和间距在内的物理参数构建响应面函数（RSF）。所建议的方法有助于以下行动。
: This paper investigates the impact of mutual inductance ( M ) on interconnect signal delay estimation according to resistance ( R ), inductance ( L ), and capacitance ( C ) in nano-scale system on a chip (SoC), suggesting a method to predict and suppress the impact. The proposed methodology fi rst calculates the di ff erence in delay between RLC and RLMC wire models for a set of parameter variations, then builds response surface functions (RSF) using physical parameters including wire width and spacing. The proposed method contributes to the following actions.