ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits
ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits
复制标题
DOI：
10.2174/187221207780832174
复制
发表时间：
2007-05
影响因子：
--
通讯作者：
M. Ker;Yuan-Wen Hsiao
中科院分区：
文献类型：
--
作者：
M. Ker;Yuan-Wen Hsiao
静电放电(ESD)保护一直是微电子技术中一个非常重要的可靠性问题，特别是在集成电路(IC)中。千兆赫兹高速输入/输出(I/O)电路的ESD保护设计一直是用CMOS工艺实现高速接口电路的关键挑战之一。传统的I/O焊盘上的片上ESD保护电路经常对高速I/O电路造成不可接受的性能降级。因此，ESD保护电路的设计必须使对高速接口电路的负面影响降至最低，并保持足够高的ESD稳健性。本文论述了高速I/O电路的ESD保护设计考虑因素，并介绍和讨论了与高速I/O电路的片上ESD保护设计相关的专利。
Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed.