Proposal and Realization of Vertical GaN Nanowire Static Induction Transistor
Proposal and Realization of Vertical GaN Nanowire Static Induction Transistor
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DOI：
10.1109/led.2018.2886246
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发表时间：
2019-02-01
影响因子：
4.9
通讯作者：
Zhang, Jing
中科院分区：
文献类型：
--
作者：
Hartensveld, Matthew;Liu, Cheng;Zhang, Jing
首次提出并实现了用于微显示的垂直氮化镓（GaN）纳米线静电感应晶体管（SIT）。采用自上而下的干法刻蚀形成高度约为1.5 μ m、直径约为350 nm的GaN纳米线，然后采用SIT制造，采用全包围栅极设计，其优点是更好的栅极控制，结合减少的表面积消耗以改善缩放和集成。需要相对低的电压来控制从源极到漏极的垂直电流。I-on与I-off之比测量为2 x 10（6），这类似于之前报道的GaN鳍SIT的900倍。这些结果表明，通过使用未掺杂的GaN（其通常是用于发光二极管（LED）的模板层）的垂直纳米线SIT将使压控组件能够用于新的集成方案和微显示技术中的机会。
Vertical gallium nitride (GaN) nanowire static induction transistors (SITs) are proposed and realized for micro display for the first time. A top-down dry etch was employed to form the GaN nanowires with height of similar to 1.5 mu m and diameter of similar to 350 nm, followed by the SIT fabrication with the gate-all-around design which benefits are better gate control, combined with reduced surface area consumption for improved scaling and integration. Relatively low voltages are required for controlling the vertical current from source to drain. The I-on to I-off ratio is measured as 2 x 10(6), which is similar to 900 times larger than the previous reported GaN fin SIT. These results demonstrated that vertical nanowire SITs by the use of undoped GaN which is typically the template layer for light-emitting diodes (LEDs) will enable voltage-controlled components for new integration schemes and opportunities in micro display technology.